Buffer layer in flat panel display

ABSTRACT

In devices such as flat panel displays, an aluminum oxide layer is provided between an aluminum layer and an ITO layer when such materials would otherwise be in contact to protect the ITO from optical and electrical defects sustained, for instance, during anodic bonding and other fabrication steps. This aluminum oxide barrier layer is preferably formed either by: (1) partially or completely anodizing an aluminum layer formed over the ITO layer, or (2) an in situ process forming aluminum oxide either over the ITO layer or over an aluminum layer formed on the ITO layer. After either of these processes, an aluminum layer is then formed over the aluminum oxide layer.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is a continuation of U.S. patent applicationSer. No. 09/387,910, filed Sep.1, 1999.

REFERENCE TO GOVERNMENT CONTRACT

[0002] This invention was made with United States Government supportunder Contract No. DABT63-97-C-0001, awarded by the Advanced ResearchProjects Agency (ARPA). The United States Government has certain rightsin this invention.

BACKGROUND OF THE INVENTION

[0003] 1. Field of the Invention

[0004] This invention relates to preserving the electrical and opticalproperties of optically transparent and conductive films such as indiumtin oxide (ITO), and more particularly, to providing a buffer orprotective layer between aluminum and ITO for use in the fabrication offlat panel displays and the like.

[0005] 2. Description of the Related Art

[0006] Optically transparent and electrically conductive materials suchas indium tin oxide (ITO) find utility in flat panel display (FPD)industries such as field emission displays (FEDs), liquid crystaldisplays (LCDs), and organic light emitting devices (OLEDs), as well asin solar cells. Surface and bulk characteristics are imperative to thequality of electrical and optical properties of these and otheroptically transparent and electrically conductive films. It is thereforevery important to ensure that such films exhibit the desired surface andbulk properties such that the desired degree of transmission of visiblelight and electrical properties are obtained.

[0007] Devices incorporating ITO often use an aluminum layer depositedover the ITO. For instance, in an FED device where the faceplate isconnected to the baseplate using spacers, aluminum is often depositedover the ITO layer in the faceplate to establish sites for the bondingof misaligned spacers. More particularly, an aluminum layer is formedover the ITO layer, the aluminum layer having wells extending therein tothe surface of the ITO layer. Bond pads are provided within these wellsagainst the ITO layer at the desired spacer locations. Then, when anarray of spacers is brought against the faceplate for anodic bonding,desired spacers contained in the array will bond to the bond pads, whileother, misaligned spacers will bond to the aluminum layer. After bondingis complete, the aluminum layer with the misaligned spacers bondedthereto can be removed to leave the desired spacer configuration in theFED.

[0008] A problem with using aluminum with ITO in the above and otherapplications is that ITO is susceptible to corrosion in the presence ofaluminum. Atomic and/or ionic diffusion occurs through the aluminum tothe ITO during processes such as anodic bonding, thermal cycling,thermal diffusion processes, low energy ion implantation processes, andprocesses which include electric and/or magnetic fields. ITO isespecially susceptible to corrosion in the presence of aluminum whenexposed to alkaline or basic solutions or solvents. See, J.E.A.M. vanden Meerakker and W. R. ter Veen, J. Electrochem. Soc., vol. 139, no. 2,385 (1992). Corrosion of ITO in alkaline solutions produces SnO₃ ²⁻,which dissolves in the solution, and In metal, which forms grains at thesurface. This causes a gray opaque appearance and a disconnectionbetween the ITO and aluminum. Corrosion of the ITO can prove fatal indevices such as flat panel displays by reducing or eliminating theelectrical conductivity and optical transparency of the ITO material.This corrosion can also cause delamination of the aluminum layer fromthe ITO. Redeposition of corrosion byproducts onto the substrate leadsto additional defects, e.g., particle defects.

[0009] Furthermore, during anodic bonding of spacers to bond pads,excess oxide can change local optical properties of the adjacent ITObetween the bond pads. Optical properties may also be changed due toetching.

[0010] Accordingly, what is needed is an improved method and apparatusfor protecting the electrical and optical properties of an ITO layer andthe like when such a layer is exposed to aluminum.

SUMMARY OF THE INVENTION

[0011] Briefly stated, the needs addressed above are solved by providingan aluminum oxide layer between an aluminum layer and an ITO layer toprotect the ITO from optical and electrical defects sustained, forinstance, during anodic bonding and other fabrication steps. Thisaluminum oxide barrier layer is preferably formed either by: (1)partially or completely anodizing an aluminum layer formed over the ITOlayer, or (2) an in situ process forming aluminum oxide either over theITO layer or over an aluminum layer formed on the ITO layer. Aftereither of these processes, an aluminum layer is then formed over thealuminum oxide layer.

[0012] In accordance with one aspect of the present invention, a methodof manufacturing a tin oxide/aluminum structure is provided. The methodcomprises forming a tin oxide layer, forming an aluminum oxide layerover the tin oxide layer, and forming a top aluminum layer over thealuminum oxide layer. In one embodiment, the aluminum oxide layer isformed by anodizing aluminum. In another embodiment, the aluminum oxidelayer is formed by reactive sputtering.

[0013] In accordance with another aspect of the present invention, a tinoxide/aluminum structure is provided comprising a tin oxide layer over asubstrate, an aluminum oxide layer over the tin oxide layer, and analuminum layer over the aluminum oxide layer. In one embodiment, the tinoxide layer comprises indium tin oxide. A second aluminum layer may beprovided between the tin oxide layer and the aluminum layer.

[0014] In accordance with another aspect of the present invention, amethod of protecting an indium tin oxide layer in the presence ofaluminum is provided. An aluminum oxide layer is formed between theindium tin oxide layer and the aluminum. The aluminum oxide layer ispreferably formed either by anodizing the aluminum or by reactivesputtering.

[0015] In accordance with another aspect of the present invention, amethod of fabricating a display device structure is provided. The methodcomprises forming an indium tin oxide layer, forming an aluminum oxidelayer over the tin oxide layer, and forming an aluminum layer over thealuminum oxide layer. The structure is then exposed to an indium tinoxide-corrosive medium, such as would be used during the fabrication ofthe display device. The aluminum oxide prevents diffusion of thecorrosive medium through the aluminum layer to the indium tin oxidelayer. Once the structure is no longer exposed to the indium tinoxide-corrosive medium, the aluminum oxide and aluminum layers areremoved. In one embodiment, these layers are removed after spacers havebeen fabricated. More preferably, by using an aluminum oxide barrierlayer between the indium tin oxide layer and the aluminum layer, thealuminum oxide and aluminum layers can be removed using an etchantcomprising phosphoric acid at a temperature up to about 60° C., withoutdamaging the indium tin oxide.

[0016] In accordance with another aspect of the present invention, adisplay device structure comprises a substrate, an electricallyconductive and optically transparent layer over the substrate, analuminum oxide layer over the electrically conductive and opticallytransparent layer, and an aluminum layer over the aluminum oxide layer.In one embodiment, the aluminum oxide layer has a thickness of betweenabout 500 and 1,500 Å, and the aluminum layer has a thickness of betweenabout 4,500 and 6,000 Å.

[0017] The aluminum oxide layer preferably comprises A10 _(x)where x isbetween about 0.25 and 1.5.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 is a schematic cross-sectional view of a flat panel displayincluding a plurality of field emission devices.

[0019]FIG. 2 is an isometric view of a baseplate of a flat paneldisplay, showing an emitter set comprising a plurality of electronemission tips.

[0020]FIG. 3 is a top view of the baseplate of flat panel display ofFIG. 2, showing the addressable rows and columns.

[0021]FIG. 4 is a schematic cross-sectional view of an FED faceplatebonded to a plurality of spacers.

[0022]FIG. 5 is a schematic top view of the faceplate of FIG. 4, showingan aluminum layer deposited thereon.

[0023]FIG. 6 is a schematic top view of an array of spacers to be bondedto the faceplate of FIG. 5.

[0024]FIG. 7A is a schematic cross-sectional view of a flat paneldisplay faceplate having an aluminum layer and an aluminum oxide layerformed thereover.

[0025]FIG. 7B is a schematic cross-sectional view of a flat paneldisplay faceplate having an aluminum oxide layer formed thereover andsandwiched between two aluminum layers.

[0026]FIG. 8 is a schematic cross-sectional view of a structure havingan ITO layer for a flat panel display faceplate and the like accordingto a first preferred embodiment, with an aluminum layer formedthereover. FIG. 9 is a schematic cross-sectional view of the structureof FIG. 8, showing partial anodization of the aluminum layer.

[0027]FIG. 10 is a schematic cross-sectional view of the structure ofFIG. 9, showing the deposition of an additional layer of aluminum.

[0028]FIG. 11 is a schematic cross-sectional view of the structure ofFIG. 8, showing complete anodization of the aluminum layer.

[0029]FIG. 12 is a schematic cross-sectional view of the structure ofFIG. 11, showing the deposition of an additional layer of aluminum.

[0030]FIG. 13 is a schematic cross-sectional view of a structure havingan ITO layer formed according to a second preferred embodiment of thepresent invention, showing the formation of the ITO layer on asubstrate.

[0031]FIG. 14 is a schematic cross-sectional view of the displaystructure of FIG. 13, showing the deposition of an intermediate aluminumlayer, an aluminum oxide layer and a top aluminum layer thereover.

[0032]FIG. 15 is a schematic cross-sectional view of the displaystructure of FIG. 13, showing the deposition of an aluminum oxide layerand an aluminum layer thereover.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] The preferred embodiments describe flat panel display devices,and more particularly, fabrication of the faceplate of an FED deviceusing indium tin oxide and the like. It will be appreciated thatalthough the preferred embodiments are described with respect to FEDdevices, the methods and apparatus taught herein are applicable to otherflat panel display devices such as liquid crystal displays (LCDs),organic light emitting devices (OLEDs), plasma displays, vacuumfluorescent displays (VFDs), electroluminescent displays (ELDs), as wellas solar cells. Other devices incorporating ITO and similar materials,such as other tin oxides, are also contemplated as being within thescope of this invention, as well as any device which employs an aluminumlayer formed over an ITO or similar layer.

[0034]FIG. 1 illustrates a portion of a flat panel display, including aplurality of field emission devices. Flat panel display 10 comprises abaseplate 12 and a faceplate 14. Baseplate 12 includes substrate 16,which is preferably formed from an insulative glass material. Columninterconnects 18 are formed and patterned over substrate 16. The purposeand function of column interconnects 18 is disclosed in greater detailbelow.

[0035] Furthermore, a resistor layer 20 may be disposed over columninterconnects 18. Electron emission tips 22 are formed over substrate 16at the sites from which electrons are to be emitted, and may beconstructed in an etching process from a layer of amorphous silicon thathas been deposited over substrate 16. Electron emission tips 22 areprotrusions that may have one or many shapes, such as pyramids, cones,or other geometries that terminate at a fine point for the emission ofelectrons.

[0036] An extraction grid 24, or gate, which is a conductive structurethat supports a positive charge relative to the electron emission tips22 during use, is separated from substrate 16 with a dielectric layer26. Extraction grid 24 includes openings 28 through which electronemission tips 22 are exposed. Dielectric layer 26 electrically insulatesextraction grid 24 from electron emission tips 22 and the associatedcolumn interconnects which electrically connect the emission tips with avoltage source 30.

[0037] Faceplate 14 includes a plurality of pixels 32, which comprisecathodoluminescent material that generates visible light upon beingexcited by electrons emitted from electron emission tips 22. Forexample, pixels 32 may be red/green/blue full-color triad pixels.

[0038] Faceplate 14 further includes a substantially transparent anode34 and a glass or another transparent panel 36. Spatial supportstructures or spacers 38 are disposed between baseplate 12 and faceplate14 and prevent the faceplate from collapsing onto the baseplate due toair pressure differentials between the opposite sides of the faceplate.In particular, the gap between faceplate 14 and baseplate 12 istypically evacuated, while the opposite side of the faceplate generallyexperiences ambient atmospheric pressure.

[0039] The flat panel display is operated by generating a voltagedifferential between electron emission tips 22 and grid structure 24using voltage source 30. In particular, a negative charge is applied toelectron emission tips 22, while a positive charge is applied to gridstructure 24. The voltage differential activates electron emission tips22, whereby a flux of electrons 40 is emitted therefrom. In addition, arelatively large positive charge is applied to anode 34 using voltagesource 30, with the result that a flux of electrons 40 strikes thefaceplate. The cathodoluminescent material of pixels 32 is excited bythe impinging electrons, thereby generating visible light. Thecoordinated activation of multiple electron emission tips over the flatpanel display 10 may be used to produce a visual image on faceplate 14.

[0040]FIGS. 2 and 3 further illustrate conventional field emissiondevices. In particular, electron emission tips 22 are grouped intodiscrete emitter sets 42, in which the bases of the electron emissiontips in each set are commonly connected. As shown in FIG. 3, forexample, emitter sets 42 are configured into columns (e.g., C₁-C₂) inwhich the individual emitter sets 42 in each column are commonlyconnected.

[0041] Additionally, the extraction grid 24 is divided into gridstructures, with each emitter set 42 being associated with an adjacentgrid structure. In particular, a grid structure is a portion ofextraction grid 24 that lies over a corresponding emitter set 42 and hasopenings 28 formed therethrough. The grid structures are arranged inrows (e.g., R₁-R₃) in which the individual grid structures are commonlyconnected in each row. Such an arrangement allows an X-Y addressablearray of grid-controlled emitter sets. The two terminals, comprising theelectron emission tips 22 and the grid structures, of the three terminalcold cathode emitter structure (where the third terminal is anode 34 infaceplate 14 of FIG. 1) are commonly connected along such columns androws, respectively, by means of high-speed interconnects. In particular,column interconnects 18 are formed over substrate 16, and rowinterconnects 44 are formed over the grid structures.

[0042] In operation, a specific emitter set is selectively activated byproducing a voltage differential between the specific emission set andthe associated grid structure. The voltage differential may beselectively established through corresponding drive circuitry thatgenerates row and column signals that intersect at the location of thespecific emitter set. Referring to FIG. 3, for example, a row signalalong row R₂of the extraction grid 24 and a column signal along columnC, of emitter sets 42 activates the emitter set at the intersection ofrow R₂and column C₁. The voltage differential between the grid structureand the associated emitter set produces a localized electric field thatcauses emission of electrons from the selected emitter set.

[0043] Further details regarding FED devices are disclosed in assignee'scopending application entitled FIELD EMISSION DEVICE WITH BUFFER LAYERAND METHOD OF MAKING, application Ser. No. 09/096,085, filed Jun.11,1998, now U.S. Pat. No. 6,211,608, and U.S. Pat. No. 5,372,973, both ofwhich are hereby incorporated by reference in their entirety.

[0044]FIG. 4 illustrates more particularly a portion of a faceplate ofan FED device fabricated according to a preferred embodiment of thepresent invention. The faceplate 14, shown upside-down relative to thefaceplate of FIG. 1, includes a substrate 36 comprising a glasssubstrate 48, a first SiN_(x) layer 46 formed on one side of the glasssubstrate 48, and a second SiN_(x) layer 50 formed on the other side ofthe glass substrate 48. The first SiN_(x) layer 46 represents theviewing side of the faceplate 14, and is preferably about 500 to 2000 Åthick. The glass layer 48 is preferably soda lime glass or borosilicateglass, and preferably has a thickness between about 0.5 and 5 mm. Thesecond SiN_(x) layer 50 is an antireflective layer preferably about 500to 2000 Å thick. In one embodiment, both the first and second SiN_(x)layers are more preferably Si₃N₄.

[0045] A black matrix grill 52 is preferably formed over the SiN_(x)layer 50. This grill 52 is preferably made of sputtered amorphous Si,and defines open regions for phosphor layer 54. The grill 52 preferablyhas a thickness of between 3000 and 20,000 Å, with the openings in thegrill preferably created by using an etchant such as an HNO₃, HF, aceticacid mixture to etch the amorphous silicon, or KOH/IPA mixtures.

[0046] The transparent anode 34 of FIG. 1 is preferably a layer ofindium tin oxide 56 as shown in FIG. 4. The ITO layer 56 is preferablyformed over the black matrix Si layer 52 and over the SiN_(x) layer 50.The ITO layer 56 is preferably deposited using physical vapordeposition, for example DC sputtering, and has a thickness preferablybetween about 2000 and 5000 Å. The applied voltage across the ITO layeris preferably about 1000 to 3000 DC volts.

[0047] Bonding pads 58 are preferably distributed around the faceplate14, as shown in FIG. 4 and in a top view illustrated in FIG. 5 (withaluminum layer 62 also shown, as described below). These bonding pads 58are located over the black matrix grill 52 and the ITO layer 56 andprovide the location for bonding the spacers 38 to the faceplate 14. Thebond pads 58 are preferably made of silicon, and preferably have asurface area when viewed from above of about 35×35 Jim. As shown in FIG.5, the bonding pads 58 are preferably alternatingly staggered across thefaceplate so that the spacers 38 bonded thereon are also spaced in astaggered configuration. It will be appreciated that bond pads 58 may belocated in various other configurations on the faceplate 14.

[0048] As shown in FIGS. 4 and 5, glass spacers 38 are bonded to thefaceplate 14 at bond pads 58 to form the spacers between the faceplate14 and baseplate 12 (not shown). These spacers 38 are more preferablymade of a soda lime silicate glass or borosilicate glass. Glassescontaining oxides of Sl, Pb, Na, K, Ba, Al, and Ag may also be used.

[0049] Bonding of the spacers to the faceplate is preferablyaccomplished using anodic bonding, although other types of bonding suchas adhesive bonding may also be used.

[0050] Although the bond pads are preferably alternatingly staggeredaround the faceplate 14 as shown in FIG. 5, it is preferred in oneembodiment to attach spacers to the faceplate 14 using a uniform array60 of spacers, such as shown in FIG. 6, which contains more spacers thanthere are bond pads 58. Thus, the array 60 not only contains the spacers38 which are to be anodically bonded to the bond pads 58, but it alsocontains misaligned spacers 66 which will not be bonded to the bond pads58. The misaligned spacers are instead anodically bonded to asacrificial aluminum layer 62 formed over the faceplate 14, asillustrated in FIGS. 7A and 7B and described in further detail below. Amatrix glass material is used to keep the spacers in the proper patternuntil after they are selectively removed after anodic bonding. In oneembodiment, after bonding the matrix glass is removed by etchingpreferably using an HNO₃/H₂O or HCl/HNO₃/H₂O or HCl/H₂O mixture. Then,the bulk of the aluminum is removed preferably using HNO₃/H₃PO₄/aceticacid mixture. KOH or NaOH is then preferably used to remove themisaligned spacers 66. The advantages of the uniform array 60 includeits simplicity of design as well as lower cost. Furthermore, becauseanodic bonding occurs at temperatures, for example, of about 450° C., auniform array of spacers is desired to create a more uniform stressdistribution when the structure is subsequently cooled.

[0051] As shown in FIGS. 5, 7A and 7B, the aluminum layer 62 has wells64 to permit access for the aligned spacers 38 to the bonding pads 58.Then, when the array 60 of spacers 38 is brought to the faceplate 14 foranodic bonding, spacers 38 are bonded to the bond pads 58 within thewells 64, while the misaligned spacers 66 are bonded to the aluminumlayer 62, as shown in phantom in FIG. 5. During subsequent processing ofthe faceplate, this aluminum layer 62 is removed, along with themisaligned spacers 66 to leave the desired spacer arrangement.

[0052]FIG. 7A illustrates generally the structure of the desiredaluminum layer over the faceplate 14 for use in the anodic bondingprocedure described above. A barrier layer 68, preferably formed ofaluminum oxide and described in further detail below, is first formedover the ITO layer 56. Other processes may use barrier layers of SiNe(nitride) or SiO₂ (oxide) between the aluminum and the ITO. However,removal of these layers requires either dry etching techniques whichpose throughput limitations (especially for large area devices) as wellas ion damage to the ITO or wet etching techniques which also damage theITO film. For example, etching of nitrides requires temperatures greaterthan 150° C. and highly concentrated phosphoric acid, which damages andetches ITO. Oxide generally requires HF based wet etchants which alsodamage and etch ITO. Furthermore, a SiN_(x) film itself has pinholesallowing diffusion, thereby causing corrosion when exposed to certainwet chemistries during lithography and etch.

[0053] An aluminum layer 62 is formed over the barrier layer 68, whichextends above the ITO layer 56 approximately the same height as that ofthe bond pads 58. FIG. 7B illustrates another embodiment in which twoaluminum layers 62 a and 62 b sandwich the aluminum oxide layer 68.

[0054] In both FIGS. 7A and 7B, wells 64 are preferably formed throughthe aluminum layer 62 (62 a and 62 b in FIG. 7B) and barrier layer 68down to the ITO layer 56. These wells 64 are staggered in the desiredconfiguration according to where the bonding pads 58 and spacers 38 areto be located, as shown in FIG. 5. In one embodiment, the wellspreferably have a bottom surface area of about 45×45 μm. After anodicbonding is complete, the barrier layer 68 and aluminum layer 62 orlayers 62 a and 62 b are removed, giving the faceplate 14 the structureshown in FIG. 4.

[0055] FIGS. 8-15 illustrate more particularly the formation thealuminum oxide barrier layer 68 illustrated in FIGS. 7A and 7B. FIG. 8illustrates schematically a portion of the faceplate 14 wherein the ITOlayer 56 is formed over a substrate 36. This substrate 36 may includethe SiN_(x) layers 46 and 50 and glass layer 48 described above, theblack matrix layer 52, or any other substrate as would be known to oneof skill in the art. The ITO layer 56 is preferably deposited over thesubstrate 36, and an aluminum layer 62 a is formed over the ITO layer56.

[0056] The aluminum layer 62 a illustrated in FIG. 8 is preferablydeposited using DC sputtering as a pressure of about 1-10 mTorr at apower of about 2,000 to 10,000 watts. Pure Ar gas is used at a carrier,flowing at a rate of about 10 to 800 sccm. The substrate temperature ispreferably between about 100 and 400° C. It will be appreciated that thealuminum layer 62 can be formed by a variety of methods, including RFsputtering, DC sputtering, ion beam sputtering, these and other methodsbeing known to one of ordinary skill in the art.

[0057]FIG. 9 illustrates the formation of an aluminum oxide barrierlayer 68 over the ITO layer 56. In one embodiment, the aluminum layer 62a is partially anodized to form an Al₂O₃ layer 68. Anodizationpreferably occurs by a process such as electrolytic anodization, a wetoxidizing agent such as H₂O₂, or an oxygen plasma. In one preferredembodiment, electrolytic anodization is used for a non in situ process,examples of which are given in Ching-Fa Yeh et al., in. Japan J. Appl.Phys. vol. 32 (1993) pp. 2803-2808, part 1, no. 6A, June 1993. Thisprocess leaves the intermediate aluminum layer 62 a and the Al₂O₃ layer68 thereover. Then, as shown in FIG. 10, an additional aluminum layer 62b is deposited over the Al₂O₃ layer 68, thereby generally forming thelayered structure shown in FIG. 7B. This layered structure protects theITO layer 56 from damage due to ion diffusion through the aluminum. Thestructure also allows for a good electrical contact between Al and ITO.The sandwiched buffer layer 68 of Al₂O₃ further suppresses topsidehillocks in the top aluminum layer 62 b,because the presence of thebarrier layer 68 minimizes the aluminum grain size in the layer 62 b.

[0058]FIG. 11 illustrates another preferred embodiment for forming analuminum oxide barrier layer. The aluminum layer 62 a of FIG. 8 ispreferably completely anodized, as shown in FIG. 11 to form an Al₂O₃layer 68. An aluminum layer 62 is formed over the Al₂O₃ layer 68 asshown in FIG. 12, preferably using a sputtering technique as describedabove. The resulting structure as shown in FIG. 12 may be used to formthe structure shown in FIG. 7A. The barrier layer 68 in this structureprotects the ITO layer 56 from damage due to ion diffusion andsuppresses hillock formation. In this structure, the aluminum layer 62and the ITO layer 56 are electrically isolated.

[0059] FIGS. 13-15 illustrate another embodiment using in situ methodsfor protecting an ITO layer 56 from damage due to exposure to analuminum layer. As shown in FIG. 13, an ITO layer 56 is formed directlyover a substrate 36. In one embodiment, as shown in FIG. 14, an aluminumlayer 62 a is deposited over the ITO layer 56, preferably in situ by aphysical vapor deposition (PVD) process as described above or chemicalvapor deposition (CVD). Then, an Al₂O₃ layer 68 is deposited over thealuminum layer 62 a. In one embodiment, the Al₂O₃ layer 68 is depositedby reactive sputtering (PVD) with an aluminum target and O2/Ar gases. Inthis embodiment, deposition occurs by RF magnetron sputtering at apressure of about 1-15 mTorr at a power of 1,000 to 6,500 watts. Amixture of Ar (94%) and O₂ ° (6%) flows into the chamber at a rate ofabout 10-800 sccm. The substrate temperature is preferably about 100 to400° C. In another embodiment, sputtering may occur with an Al₂O₃ targetand an Ar/O₂ratio of about 1. Chemical vapor deposition (CVD) or metalorganic vapor phase deposition (MOVPD) with gases such astrimethylaluminum and hydrogen peroxide may also be used.

[0060] Then, an aluminum layer 62 b is deposited over the Al₂O₃ layer,preferably using a method such as described above. More particularly,when using a sputtering technique to form the Al₂O₃ layer 68, thealuminum layer may be formed simply by turning off the O₂ gas flow. Thestructure illustrated in FIG. 14 corresponds substantially to thestructure illustrated in FIG. 10, as well as in FIG. 7B.

[0061] As shown in FIG. 15, the Al₂O₃ layer 68 can be grown directlyover the ITO layer 56, followed by growth of an aluminum layer 62 usingthe in situ methods described above. The structure shown in FIG. 15corresponds to the structure formed by complete anodization shown inFIG. 12, as well as the structure shown in FIG. 7A.

[0062] The aluminum oxide barrier layers 68 illustrated in FIGS. 10, 12,14 and 15 should be thick enough to prevent a conductive path betweenthe top aluminum layer 62 or 62 b and the ITO layer 56. The layer 68preferably has a thickness ranging from about 100 to 10,000 Å, morepreferably about 300 to 5,000 Å, and even more preferably about 500 to1,500 Å. The desired thickness of the layer 68 also depends on thesurface topography of the underlying layers, which in one embodiment,may have a roughness of about 500 Å. Roughness of this magnitude wouldnecessitate an aluminum oxide thickness greater than 500 Å.

[0063] The thickness of the top aluminum layer 62 b in FIGS. 10 and 14,and the aluminum layer 62 in FIGS. 12 and 15, is preferably betweenabout 4,000 and 10,000 Å. In an embodiment where the aluminum layer 62or 62 b is used for anodic bonding to spacers, the thickness of thislayer should be great enough to allow anodic bonding. For the displaydevice structures shown in FIGS. 7A and 7B, the total thickness of thealuminum oxide and aluminum layers should be approximately equal to thethickness of the bond pads 58.

[0064] Although the preferred embodiments above have been described asusing a barrier layer of Al₂O₃, the aluminum oxide barrier layer 68 maygenerally be represented as A10_(x,) where x is between about 0.25 and1.5. It will be appreciated that both the aluminum and aluminum oxidelayers may be formed by a variety of methods as would be known to oneskilled in the art. Furthermore, when sputtering is used, the choice oftarget may varied, using for example, A1, Al₂O ₃, Al-Si alloy, and A1doped with rare earth elements. The mixing ratio of Ar and O₂ gas mayalso be varied.

[0065] The aluminum oxide layer illustrated and described in theembodiments above acts as a protective barrier preventing surface andbulk property damage of the ITO, or other films including other tinoxides, during downstream thermal processes such as anodic bonding andthermal diffusion processing. In particular, the aluminum oxide barrierprovides protection to the ITO layer by preventing diffusion of atomsand ions into the ITO during thermal cycling, thermal diffusionprocesses, low energy ion implantation processes, and processes whichinvolve electric and/or magnetic fields.

[0066] For example, the Al₂O₃ layer 68 described above protects the ITOlayer 56 from optical and electrical defects sustained during anodicbonding of structures onto the aluminum located on the film side of theITO. These processes typically operate at 500 V at 450° C. If no barrieris used between the aluminum and ITO, patterned defects in the ITO arisefrom ionic diffusion from the structures through the aluminum duringanodic bonding of structures to the substrate, thus causing damage tothe ITO.

[0067] Another advantage of using aluminum oxide as a barrier layer,especially in comparison to SiN_(x) and SiO₂, is that aluminum oxideallows for greater throughput because it permits the use of wetprocessing of large area devices or panels. For example, during removalof the aluminum layer 62 or layers 62 a and 62 b in FIGS. 7A and 7B,respectively, to form the structure of FIG. 4, if a barrier layer ofSiN_(x) is used between the aluminum and the ITO, dry etching isrequired because the conventional etchant, H₃PO₄, causes damage to ITOat temperatures greater than about 150° C. Aluminum oxide, by contrast,can be etched at lower temperatures, thereby preventing damage to theITO and enabling faster processing times. For instance, the aluminumoxide can be selectively etched over ITO using chemicals such asmoderately concentrated phosphoric acid or phosphoric acid/nitricacid/acetic acid combinations at moderate temperatures, up to about 60°C. These etchants at these lower temperatures do not cause significantdamage to the ITO.

[0068] Further advantages of the barrier layer described above includethat the aluminum oxide and aluminum layers can be deposited in situ andetched in one wet process step. Moreover, an aluminum oxide barrierprevents aluminum hillocks from pinning into the ITO film as well as theassociated surface deformations of the ITO which are caused by hillocks.The Al₂O₃ barrier also provides a good adhesion layer for aluminum tothe substrate and reduces film stress. All of the factors above increasethe yield of the fabricated devices.

[0069] The embodiments illustrated and described above are providedmerely as examples of certain preferred embodiments of the presentinvention. Other changes and modifications can be made from theembodiments presented herein by those skilled in the art withoutdeparture from the spirit and scope of the invention, as defined by theappended claims.

What is claimed is:
 1. A method of fabricating a display devicestructure, comprising: forming a tin oxide layer; forming an aluminumoxide layer over the tin oxide layer; and forming an aluminum layer overthe aluminum oxide layer after the aluminum oxide layer has been formedover the tin oxide layer.
 2. The method of claim 1, wherein the tinoxide layer is indium tin oxide.
 3. The method of claim 1, wherein thealuminum oxide layer is formed by anodizing aluminum.
 4. The method ofclaim 3, wherein the aluminum is anodized by a process selected from thegroup consisting of using electrolytic anodization, a wet oxidizingagent and an oxygen plasma.
 5. The method of claim 3, wherein thealuminum is partially anodized to form a sandwiched aluminum layerbetween the tin oxide layer and the aluminum oxide layer formed byanodization.
 6. The method of claim 3, wherein the aluminum iscompletely anodized.
 7. The method of claim 1, further comprisingdepositing an intermediate aluminum layer over the tin oxide layer priorto forming the aluminum oxide layer.
 8. The method of claim 7, whereinthe intermediate aluminum layer is formed by sputtering.
 9. The methodof claim 1, wherein the aluminum oxide layer is formed by reactivesputtering.
 10. The method of claim 1, wherein the aluminum layer isformed by sputtering.
 11. The method of claim 1, wherein the aluminumoxide later comprises AlO_(x), where x is between about 0.25 and 1.5.12. The method of claim 1, wherein the aluminum layer and aluminum oxidelayer cover the indium tin oxide layer except for regions where thereare wells formed in the indium tin oxide layer.